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cy7c1019cv33 1 mbit (128k x 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05130 rev. *i revised october 13, 2010 features temperature ranges ? industrial: ?40c to 85c ? automotive-a: ?40c to 85c pin and function compatible with cy7c1019bv33 high speed ? t aa = 10 ns cmos for optimum speed and power data retention at 2.0v center power/ground pinout automatic power down when deselected easy memory expansion with ce and oe options available in pb-free and non pb -free 48-ball vfbga, 32-pin tsop ii and 400-mil soj package functional description the cy7c1019cv33 is a high performance cmos static ram organized as 131,072 words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ), and tristate drivers. this device has an automatic power down feature that significantly reduces power consumption when deselected. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 16 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pi ns will appear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low, and we low). 14 15 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer power down we oe i/o 0 i/o 1 i/o 2 i/o 3 128k x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 11 a 13 a 12 a a 10 ce a a 16 a 9 logic block diagram [+] feedback
cy7c1019cv33 document #: 38-05130 rev. *i page 2 of 12 selection guide description -10 (industrial/ auto-a) -12 (industrial) -15 (industrial) unit maximum access time 10 12 15 ns maximum operating current 80 75 70 ma maximum standby current 5 5 5 ma pin configuration figure 1. 48-ball vfbga (top view) [1] figure 2. 32-pin soj/tsop ii (top view) [1] we v cc a 9 a 16 nc a 4 a 2 a 1 ce nc i/o 0 i/o 1 a 5 a 0 nc nc nc i/o 2 i/o 3 v ss a 10 a 3 oe v ss nc i/o 7 nc nc a 13 a 7 a 6 nc v cc i/o 6 nc nc nc i/o 4 i/o 5 a 8 a 11 a 14 a 12 a 15 nc nc nc 3 2 6 5 4 1 d e b a c f g h nc 1 2 3 4 5 6 7 8 9 10 11 14 19 20 24 23 22 21 25 28 27 26 12 13 29 32 31 30 16 15 17 18 a 7 a 1 a 2 a 3 ce i/o 0 i/o 1 v cc a 13 a 16 a 15 oe i/o 7 i/o 6 a 12 a 11 a 10 a 9 i/o 2 a 0 a 4 a 5 a 6 i/o 4 v cc i/o 5 a 8 i/o 3 we v ss a 14 v ss note 1. nc pins are not connected on the die. [+] feedback
cy7c1019cv33 document #: 38-05130 rev. *i page 3 of 12 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ...............................?65c to +150c ambient temperature with power applied ........................ ..................?55c to +125c supply voltage on v cc to relative gnd [2] .....?0.5v to +4.6v dc voltage applied to outputs in high-z state [2] .................................... ?0.5v to v cc + 0.5v dc input voltage [2] ................................ ?0.5v to v cc + 0.5v current into outputs (low)....... .................................. 20 ma static discharge voltage....... ........... ............ .............. >2001v (per mil-std-883, method 3015) latch up current...................................................... >200 ma operating range range ambient temperature v cc commercial 0c to +70c 3.3v ? 10% industrial ?40 ? c to +85 ? c 3.3v ? 10% automotive-a ?40 ? c to +85 ? c 3.3v ? 10% electrical characteristics over the operating range parameter description test conditions ?10 (industrial/ auto-a) ?12 (industrial) ?15 (industrial) unit min max min max min max. v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 v v ih input high voltage 2.0 v cc + 0.3 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il input low voltage [2] ?0.3 0.8 ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ?1 +1 ?1 +1 ? a i oz output leakage current gnd < v i < v cc , output disabled ?1 +1 ?1 +1 ?1 +1 ? a i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 80 75 70 ma i sb1 automatic ce power down current ?ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 15 15 15 ma i sb2 automatic ce power down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 555ma capacitance [3] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = 5.0v 8pf c out output capacitance 8 pf notes 2. v il (min.) = ?2.0v for pulse durations of less than 20 ns. 3. tested initially and after any design or process changes that may affect these parameters. [+] feedback
cy7c1019cv33 document #: 38-05130 rev. *i page 4 of 12 figure 3. ac test loads and waveforms [4] switching characteristics over the operating range [5] parameter description -10 (industrial/ auto-a) -12 (industrial) -15 (industrial) unit min max min max min max read cycle t rc read cycle time 10 12 15 ns t aa address to data valid 10 12 15 ns t oha data hold from address change 3 3 3 ns t ace ce low to data valid 10 12 15 ns t doe oe low to data valid 56 7 ns t lzoe oe low to low z 00 0 ns t hzoe oe high to high z [6, 7] 56 7 ns t lzce ce low to low z [7] 33 3 ns t hzce ce high to high z [6, 7] 56 7 ns t pu [8] ce low to power up 00 0 ns t pd [8] ce high to power down 10 12 15 ns write cycle [9, 10] t wc write cycle time 10 12 15 ns t sce ce low to write end 8 9 10 ns t aw address setup to write end 8 9 10 ns t ha address hold from write end 0 0 0 ns t sa address setup to write start 0 0 0 ns t pwe we pulse width 78 10 ns t sd data setup to write end 5 6 8 ns t hd data hold from write end 0 0 0 ns t lzwe we high to low z [7] 33 3 ns t hzwe we low to high z [6, 7] 56 7 ns notes 4. ac characteristics (except high-z) for all speeds are tested using the thevenin load shown in section (a) in figure 3 . high-z characteristics are tested for all speeds using the test load shown in section (c) in figure 3 . 5. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v. 6. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (d) of figure 3 . transition is measured ? 500 mv from steady-state voltage. 7. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 8. this parameter is guaranteed by design and is not tested. 9. the internal write time of the me mory is defined by the overlap of ce low and we low. ce and we must be low to initiate a write, and the transition of any of these signals can terminate the write. the input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write. 10. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 90% 10% 3.0v gnd 90% 10% all input pulses 3.3v output 30 pf (a) r 317 ? r2 351 ? rise time: 1 v/ns fall time: 1 v/ns (b) 3.3v output 5 pf (c) r 317 ? r2 351 ? high-z characteristics: [+] feedback
cy7c1019cv33 document #: 38-05130 rev. *i page 5 of 12 switching waveforms figure 4. read cycle no. 1 [11, 12] figure 5. read cycle no. 2 (oe controlled) [12, 13] figure 6. write cycle no. 1 (ce controlled) [14, 15] notes 11. device is continuously selected. oe , ce = v il . 12. we is high for read cycle. 13. address valid prior to or coincident with ce transition low. 14. data i/o is high impedance if oe = v ih . 15. if ce goes high simultaneously with we going high, the output remains in a high impedance state. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce icc isb impedance address data out v cc supply current t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce address we data i/o [+] feedback
cy7c1019cv33 document #: 38-05130 rev. *i page 6 of 12 figure 7. write cycle no. 2 (we controlled, oe high during write) [14, 15] figure 8. write cycle no. 3 (we controlled, oe low) [15] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 16 data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 16 truth table ce oe we i/o 0 ?i/o 7 mode power h x x high z power down standby (i sb ) l l h data out read active (i cc ) l x l data in write active (i cc ) l h h high z selected, outputs disabled active (i cc ) note 16. during this period the i/os are in the output state and input signals should not be applied. [+] feedback
cy7c1019cv33 document #: 38-05130 rev. *i page 7 of 12 ordering information speed (ns) ordering code package diagram package type operating range 10 cy7c1019cv33-10zxa 51-85095 32-pin tsop ii (pb-free) automotive-a 12 cy7c1019cv33-12zxc 51-85095 32-pin tsop ii (pb-free) commercial 15 cy7c1019cv33-15vxc 51-85033 32-pin 400-mil molded soj (pb-free) commercial 10 cy7c1019cv33-10zxat 51-85095 32-pin tsop ii (pb-free) automotive-a 12 CY7C1019CV33-12ZXCT 51-85095 32-pin tsop ii (pb-free) commercial 15 cy7c1019cv33-15vxct 51-85033 32-pin 400- mil molded soj (pb-free) commercial ordering code definitions x = t or blank t = tape and reel; blank = tube temperature range: x = a or c a = automotive-a; c = commercial package type: xx = zx or vx zx = 32-pin tsop ii (pb-free) vx = 32-pin 400-mil molded soj (pb-free) speed grade (xx = 10 ns / 12 ns / 15 ns) v33 = 3.3 v process technology ? 0.16 m 1019 = part identifier cy7c = cypress srams cy7c 1019 c - xx xx x v33 x [+] feedback
cy7c1019cv33 document #: 38-05130 rev. *i page 8 of 12 package diagrams figure 9. 32-pin (400-mil) molded soj 51-85033 *c [+] feedback
cy7c1019cv33 document #: 38-05130 rev. *i page 9 of 12 figure 10. 32-pin tsop ii 51-85095 *a [+] feedback
cy7c1019cv33 document #: 38-05130 rev. *i page 10 of 12 figure 11. 48-ball vfbga (6 x 8 x 1 mm) 51-85150 *f [+] feedback
cy7c1019cv33 document #: 38-05130 rev. *i page 11 of 12 document history page document title: cy7c1019cv33 1 mbit (128k x 8) static ram document number: 38-05130 rev. ecn no. submission date orig. of change description of change ** 109245 12/16/01 hgk new data sheet *a 113431 04/10/02 nsl ac test l oads split based on speed *b 115047 08/01/02 hgk added tsop ii package and i temp. improved i cc limits *c 119796 10/11/02 dfp updated standby current from 5 na to 5 ma *d 123030 12/17/02 dfp updated truth table to reflect single chip enable option *e 419983 see ecn nxr added 48-ball vfbga package added lead-free parts in ordering information table replaced package name column with package diagram in the ordering information table *f 493543 see ecn nxr removed 8 ns speed bin from product offering added note #1 on page #2 changed the description of i ix from input load current to input leakage current in dc electrical characteristics table removed i os parameter from dc electrical characteristics table updated ordering information *g 2761448 09/09/2009 vkn included automotive-a information *h 2897691 03/23/2010 rame updated ordering information updated package diagrams *i 3057593 10/13/2010 pras updated ordering information and added ordering code definitions . updated package diagrams . [+] feedback
document #: 38-05130 rev. *i revised october 13, 2010 page 12 of 12 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1019cv33 ? cypress semiconductor corporation, 2001-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com [+] feedback

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